The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to sub-lithographic magnetic tunnel junctions for magnetic random access memory (MRAM) devices.
MRAM devices such as spin-transfer torque MRAM (STT MRAM) are well suited for many mainstream applications, particularly as a storage technology, because it delivers the high performance of DRAM and SRAM, has the low power and low cost of flash memory, and leverages existing CMOS manufacturing techniques and processes. The magnetic tunnel junctions (MTJs) in these MRAM devices can be switched between a low resistance state (0) and a high resistance state (1) by applying a voltage and sending a current through the device. Because it is non-volatile, STT-MRAM will also retain its data indefinitely when the power is lost or completely turned off. Moreover, it is desirable that the device be able to switch at low currents to minimize power consumption as well as to enable the device to be integrated with the most advanced CMOS circuitry for which supply voltages are low. One way to lower the switching current and improve the efficiency of an STT MRAM device is to reduce its size. With the best available lithographic printing available, as well as the best processes, the present size of the MTJ is generally limited to about 35 nm in order to fabricate large memory arrays reproducibly and reliably.